Why use an Integrated Design Approach?
In prior blog posts, we’ve talked about why the future of compound semiconductor technologies, especially those that can benefit from CMOS integration (i.e. displays, wireless communication, etc.), must be made via CMOS end-to-end manufacturing. This is to ensure scalability and reduce the need for additional capital expenses to bring compound semiconductor technologies to market. Solutions that attempt to create their own supply chain rather than adopting CMOS manufacturing will struggle to scale to the massive volumes required by consumer technologies. Keeping with our core tenet that CMOS end-to-end manufacturing is a necessity, nsc’s technology and the way we design circuits and systems are adapted to be closely in line with the CMOS design process to maintain compatibility with the CMOS foundry infrastructure. By doing so, we have realized key advantages of the integrated design process beyond the immediate advantages of CMOS and III-V alone. In other words, it is a case where the whole is indeed greater than the sum of its parts.
How does the CMOS design environment work?
To understand why nsc has some unmatched advantages over incumbent approaches for creating III‑V and CMOS systems, we need to first take a brief look at how the CMOS foundry and design process works. Designing a CMOS chip is extraordinarily complex: these chips contain millions of individual devices all switching/regulating in perfect harmony to create the desired result. It involves precisely choosing the parameters of each individual device and determining how they are connected to achieve a successful design outcome. Because of this complexity, CMOS chips are designed using electronic design automation (EDA) software that helps to minimize human error and accelerate the design process. With hundreds of manufacturing process steps and dozens of distinct types of silicon devices available in a single foundry process node, the design and manufacturing of complex systems requires an enormous amount of information to be communicated between foundries that fabricate the chips and designers who ideate circuits for these chips. This is done via a process design kit (PDK), which CMOS foundries provide to designers, containing the fundamental building blocks of a technology process node, namely the devices that are offered, design rules, and design acceleration tools. The designers use this PDK to design their circuits and create the physical layout that is submitted to the foundry for fabrication.
The PDK helps provide assurance to both designers and foundries that (1) the designs submitted are indeed manufacturable and (2) circuits will work as intended. For the former, foundries provide a set of design rules, which can be, for example, physically how close together two devices can be, or how wide the metal traces should be drawn to interconnect the devices. For the latter, this is done via P-Cell. Each device offered in a technology (often called a P-Cell) includes a schematic symbol, physical layout, and device model card which are the essential components for simulating the behavior and performance of individual devices. These cards typically define the lower and upper bounds of acceptable performance for a device. Designers can use these to test the functions of the integrated circuit with simulations across the range of acceptable performance, also known as process corners. So, using the PDK in the EDA environment is key in designing reliable and complex systems with high yield.
In addition to the devices and rules that the designers must follow, design acceleration and verification tools are also included in the PDK to minimize the risk of human error and accelerate the design process. As designs have reached huge sizes, these tools have become critical to accelerate the design process and reduce design cycle time and manpower requirements.
How does nsc create an integrated design environment?
While foundry-provided CMOS PDKs provide all the necessary information for designing a CMOS chip, nsc’s integration scheme brings the distance between CMOS and III-V devices to the micron-scale rather than on separate chips. This integration and use of the modern foundry model requires nsc to create a CMOS+III-V integrated PDK (iPDK), which seamlessly enables CMOS + III-V circuit design, simulation, layout and verification for our design team.
It’s key to note that although nsc is enabling new functionality with the addition of III-V devices, it does so by adhering to commercial, established approaches for circuit design and verification to maintain compatibility with existing EDA tools, which is core to the aforementioned tenet.
The iPDK contains all of the information about the selected CMOS foundry process, as well as the necessary information pertaining to the III-V devices. The iPDK is created by packaging the CMOS foundry PDK with proprietary III-V P-Cells, design acceleration tools, and design rule files to enable a seamless design flow that enables designers well-versed in CMOS design to quickly adapt to the new capabilities of the CMOS+III-V process, without needing to learn a completely new design flow with the EDA software. III-V devices of course do not follow the electrical behavior of CMOS devices and therefore need different device models as well.
nsc uses both proprietary and open-source models to predict the electrical behavior of III-V devices. The iPDK enables designers well-versed in CMOS to design cutting edge chips with new functionality beyond what can be imagined with CMOS or III-V alone.
What advantages does an Integrated Design Process provide?
Despite the necessary role of the iPDK to ensure manufacturability in the CMOS foundry environment, there are other critical advantages that are enabled though a unified design process.
First is design certainty and verification. One of the largest challenges in designing systems that use multi-chiplet advanced packaging techniques is that it is difficult to validate that one chiplet with an unknown process corner will always work with another chiplet with an unknown process corner. Currently, most chiplet based systems communicate via digital signals (i.e. '0's or '1's). However, tight densities of interconnects between chiplets in some applications may require analog signals (highly specific voltages or currents e.g. 1.269 V or 0.52 mA) instead. The challenge with this is that analog signals are much more difficult to communicate than digital signals due to the accuracy required. This is made even more difficult by a greater dependence on process corners and a greater sensitivity to any slight process drift. However, when we integrate CMOS and III-V devices on the same wafer and design an integrated single chip system using an iPDK, process corners gain a degree of correlation meaning they tend to drift together in a predictable way. This correlation is due to using the same processes (equipment, facilities, thermal treatments etc.) for a given wafer/lot. The correlation of the process corners allows designers to gain confidence that if simulation of a circuit passes the target specification for all process corner, then the physical chip has a high chance of in-spec operation.
Second is performance. When trying to push the performance limits of a given technology, it is necessary to minimize design safety margins. Having a greater certainty in simulation accuracy using both CMOS and III-V devices will allow designers to push the limits of this new CMOS+ III-V platform technology. This will enable higher performance systems at a greater yield than combining discrete chiplets. The chiplet approach will always require greater margin of safety than an integrated approach.
Third is application-specific design tools. As nsc’s platform can integrate several types of III-V devices with CMOS (e.g. LEDs, HEMTs), there arises an opportunity for unique designer tool sets for different applications. For example, nsc’s PixelatedLightEngine™ solution, which combines GaN LEDs and CMOS devices, is an ideal platform for optical sensors and emitters solutions and therefore requires simulation tools that include optical information. On the other hand, RF transmitters and receivers using nsc’s CMOS + GaN HEMT process require the use of RF simulation tools such as Advanced Design System (ADS). nsc’s design infrastructure and iPDK can be integrated with many industry standard design tools and plugins, which accelerates the design process and improves design certainty.
Last is design cycle time and manpower requirements. Designing multiple chiplets will always be more time consuming than designing a single chip due to design overhead required for each chiplet. Design rule checks and layout vs. schematic checks are necessary requirements to ensure circuit functionality for each individual chip. Running these time-intensive steps on two individual chiplets, and hoping they are compatible when combined at the packaging stage, will extend the design cycle and increase upfront NRE costs.
Through these critical advantages, nsc will make novel chips for customers enabling multiple high growth applications. If you would like to learn more about how nsc’s iPDK helps designers to create complex CMOS + III-V circuits in our novel emerging CMOS + III-V process, email us at firstname.lastname@example.org.